Taking a shot at the dark here, maybe some other EE's from UT can help. Ok, so I'm doing this lab of desiging circuits, the requirement is that the output needs to be full voltage swing. My logic gives the correct out puts but the voltage swing isn't high enough (i.e. 4.7v when vdd is 5v). What can I add to the end of the circuit to get the swing higher?
You need to decrease the Vds of the transistors in your output stage. To do that... Remember Vds >= Vgs-Vt for saturation. Determine which side is causing you to miss your target (my guess is you're doing dynamic loading, so you've got a transistor in your amp and a transistor as the load). Change that transistor so that the required Vds is lower and you increase the swing. How to change the transistor... Remember that Id = k W/L (Vgs - Vt)^2 equation... and consider if there's anything you can do to W, L, Id (what else would it affect?) or (Vgs-Vt) to accomplish your goals? Sorry if this is not what you're looking for - I just had a project involving this stuff, too.
I think this is the greatest source of knowledge you will find anywhere on the internet. I find myself telling people new things and refering to the "Rockets site" all the time.
thx, R104. I already somewhat figured it. Just added 2 inverters at the end, and change the w/l ratio between two of them down to one and it worked. Gonna try to optimize the circuit either later tonight or tommorow.
